Gated RS Latch
This material was developed with funding from the National Science Foundation under Grant # DUE 1601612
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Q
RESET 0 or OFF
The truth table illustrates the operation of the RS Latch. The RS Latch is called a bi-state device due to the fact that it can be switched into one of two possible state SET or RESET.
1
0
0
SET 1 or ON
Not legal for both latches to be turned on
No change
Click switches on and off
CLK
S
4/5
1
Not allowed
R
OUTPUT
INPUTS
Q
Q
One way to improve the RS Latch is to control when the RS inputs listen for a signal change. By adding a pair of NAND gates to the input circuits of the RS latch, we accomplish two goals: normal rather than inverted inputs, and a third input common to both gates which can use to synchronize when the latch listens to the RS inputs. This provides for more stability and enable the latch to be synchronized to other ciruits or devices.
Clock Signal Must be HIGH to read R and S.
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Room #1
75
motion sensor
Replay Animation
(motion sensor)
Q
The Gated or Enabled RS Latch is a logic device that can only change states or latched when an enable input is true or 1. These inputs typically represent a control from a central facility. For example lets imagine the heating and air conditioning systems in a school. Each room has a thermostat that controls the cooling in each room. The school does not want to cool rooms that are not occupied. So even if the thermostat in a particular room requests the cooling, if the central control turns off the enable because the room is not occupied, no thermostat cooling request will turn on the system.
78
77
Room #2
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cool on
cool off
79
No change in output
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The clocked RS latch circuit is very similar in operation to the basic latch. The S and R inputs are normally at logic 0, and must be changed to logic 1 to change the state of the latch. However, with the third input, a new factor has been added. This input is typically designated C or CLK, because it is typically controlled by a clock circuit of some sort, which is used to synchronize several of these latch circuits with each other. The output can only change state while the CLK input is a logic 1. When CLK is a logic 0, the S and R inputs will have no effect.
Cooling