This material was developed with funding from the
National Science Foundation under Grant # DUE 1601612
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The truth table illustrates the operation of the D-type Flip Flop. The new single input is called the “D” input or “DATA” input. If this data input is held HIGH when a clock signal is applied the flip flop will be driven to the “SET” state, if the D input is held LOW when a clock signal is applied the flip flop would change and become “RESET”.
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The D- type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R inputs from being at the same logic level. Recall that one of the disadvantages of the R-S Latch is that the indereminate input condition in which both R and S are in the active condition. This is an illegal condition and can cause the latch to transition to an unpredictable state.
These logic device are design into electronic Integrated Circuits or ICs. The diagram below shows two D-Type flip-flops in one IC. This IC is labeled a 74LS74 D-Type Flip Flop
The D Flip Flop is a clocked type of flip-flops, it ensures that the active inputs (R and S) are never equal to one at the same time. D-type flip flop are constructed with an inverter added between the S and the R inputs preventing them from ever being in the same state thus preventing the illegal state. Instead a single D (Data) input is created.
One of the most common uses for a D-Type FF is as a Frequency Divider. A frequency divider reduces the input of a digital signals frequency by half. By placing a feedback loop around the D-type flip flop another type of flip-flop circuit can be constructed called a T-type flip-flop or more commonly a T-type bistable, that can be used as a divide-by-two circuit in binary counters as shown above.
Another very useful application of the D-TYPE FF is as a memory bus buffer or que. The D-TYPE FF are connected together with a single clock input signal. The individual D-INPUTs can be connect to a data bus. When data needs to be moved from one place to another a bus or series of data lines can be used to move the data. The data line on the bus each connect to a different D-Input. When the clock changes state to high, the data is captured by the 4-Bit buffer or que.